1. Field of the Invention
The present invention relates to an integrated circuit structure of the type having at least one CMOS NAND gate, as well as to a method for manufacturing such a circuit structure.
2. Description of the Prior Art
In planar silicon technology, the source, channel and drain of a MOS transistor are laterally arranged. A gate dielectric and a gate electrode are arranged at the surface of the channel region. The obtainable gate lengths of these MOS transistors as well as the obtainable packing density of integrated circuits composed of a plurality of MOS transistors are dependent on the resolution of the lithography employed and on tolerances in the structuring and adjustment. Typical gate lengths of 0.6 .mu.m are achieved in the 16M generation and typical gate lengths of 0.35 .mu.m are achieved in the 64M generation.
A further reduction of the lateral expanse is sought by improvements in the optical lithography as well as in the lacquer and etching technique. It seems questionable, however, whether transistors having channel lengths below 100 nm can be reproducibly manufactured in this way because of the limited resolution of the optical lithography and because of the increasing problems with tolerances in the structuring and adjustment.
Smaller structural sizes in planar technology can be achieved by employing electron beam lithography instead of optical lithography. Manufacturing individual, functional MOS transistors with channel lengths down to 50 nm has been achieved with an electron beam printer on a laboratory scale. Due to its low processing speed, however, electron beam lithography seems unsuitable for use in commercial scale semiconductor fabrication for economical reasons.
The problem of increased packing density particularly arises given complex logic circuits such as logic gates, since a plurality of n-channel and p-channel transistors must be insulated from one another, but must also be selectively electrically connected to one another in such circuits.
An overview of possible uses of molecular beam epitaxy is provided in the introduction to the dissertation of W. Kiunke, 1992, pp. 2-3. Uniform layers having a minimal thickness of around 1 atom layer can be produced in controlled fashion in molecular beam epitaxy. A doping of the layers in the range from 10.sup.14 cm.sup.-3 through 10.sup.20 cm.sup.-3 is possible in situ during the epitaxy by adding dopant. As an applied example, a proposal for a vertical CMOS invertor is discussed. The proposed invertor is realized as a mesa structure on a substrate. The mesa structure comprises an npnpnp layer sequence with vertical sidewalls. All vertical sidewalls of the layers are provided with a gate dielectric and with a gate electrode at one side.